China's chipmakers pay a steep price to bypass EUV limits

Export controls have blocked ASML's extreme ultraviolet lithography machines from entering China, forcing domestic foundries to rely on older deep ultraviolet equipment. This dependency creates a financial and technical burden that experts describe as a growing drag on production efficiency.

Chris Mack, co-founder and CTO of Fractilia, noted that industry standards suggest three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. However, when manufacturers require four masks to print a layer, EUV becomes the cheaper option. Each additional exposure increases the risk of defects and extends production timelines, raising the cost per unit of silicon.

SMIC has used this multiple patterning technique to advance its processes. A 2023 teardown of Huawei's Mate 60 Pro revealed its Kirin 9000S processor was built on a second-generation 7nm-class process without EUV. More recent analysis indicates SMIC's Kirin 9030 approaches the density of 5nm manufacturing, though it still lags behind TSMC and Samsung. This progress comes with physical trade-offs, as designers must add spacing around features to compensate for alignment errors, which enlarges the chip and reduces the number of dies per wafer.

The efficiency gap is most visible in the memory sector. In a June report, Morgan Stanley estimated that CXMT produces only about one-third as many bits per wafer as its Western competitors. The bank labeled lithography access a "hard ceiling" for Chinese memory development. Mack emphasized that "you don't sell wafers, you sell die," meaning lower yield rates directly impact margins when wafers cost tens of thousands of dollars each.

Despite these constraints, Chinese firms continue to expand capacity. Morgan Stanley projects CXMT will increase its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 by building new greenfield facilities. The bank also expects China's AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030. This growth assumes manufacturers accept larger dies and poorer yields while using DUV for next-generation products like HBM3e.

The long-term outlook for high-density logic chips remains constrained. Mack stated he would be "hard pressed" to believe a 3nm or 2nm node is economically viable without EUV. While DUV can still push performance in memory, the cost of extra exposures limits how far Chinese logic processes can scale against Western benchmarks.

The current strategy relies on volume and incremental improvements rather than breakthroughs in lithography. CXMT plans to move to 1-alpha DRAM using DUV, a step Morgan Stanley deems achievable. However, the persistent gap in lithography access continues to shape the financial structure of China's semiconductor industry, forcing a trade-off between cost and capability.